1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit testing.
2. Description of the Background Art
Integrated circuits designed with testability in mind may include provisions for scan testing. A scan test involves loading input scan data into a scan chain (also referred to as a “scan shift register”, using the input scan data to test logic in the device-under-test (DUT), loading the scan chain with output scan data from the logic of the DUT, reading out the output scan data from the scan chain, and analyzing the output scan data to determine whether the DUT has passed or failed the test. In contrast to so called “boundary-scan-testing”, scan tests allow for testing of logic deep in the DUT rather than just the boundaries of the DUT. Scan tests, in general, are known in the art and described in several publications including: A. Khoche, “Test Resource Partitioning for Scan Architectures using Bandwidth Matching,” 2002 IEEE Test Resource Partitioning Workshop, October 2002, pp. 1.4-1 to 1.4-8; A. Crouch, “Design-For-Test For Digital IC's and Embedded Core Systems,” Prentice Hall, 1999, pp. 93-133; and G. Maston, T. Taylor, and J. Villar, “Elements of STIL: Principles and Applications of IEEE Std. 1450,” Kluwer Academic Publishers, 2003, pp. 201-205.
A scan chain may comprise multiple, serially connected flip-flops. A scan chain may use a scan clock to time the shifting of scan data from one flip-flop to another. Input scan data may be serially loaded into the scan chain and then unloaded in parallel for testing a logic circuit. Data from the logic circuit being tested may be loaded in parallel to the scan chain and then read out as output scan data for analysis. A scan architecture may also employ multiple scan chains. There are advantages to using multiple scan chains, including reduction of test time proportional to the reduction in length of the longest scan chain. A disadvantage of using multiple scan chains is that for each scan chain, independent scan in and scan out pins are required. Scan chains and the use of multiple scan chains are also discussed by A. Khoche in the aforementioned IEEE publication “Test Resource Partitioning for Scan Architectures using Bandwidth Matching.”
A scan architecture may employ additional circuitry to reduce the number of pins needed when multiple scan chains are used. These additional circuitry are only used for test and may include broadcasting and compacting circuits. SynTest Technologies, Inc. of Sunnyvale, Calif. employs such an architecture in its Virtualscan™ tool suite.
A major disadvantage of the aforementioned scan architectures is that the added functionality and circuitry are added overhead as they are exclusively used for test purposes only. Furthermore, the added functionality and circuitry are usually not capable of supporting high-speed scan tests as they are based on conventional input/output test interfaces. Test time increases with the increase in the number of cycles to transfer the same amount of data across narrower serial in and out pins.